BEGIN:VCALENDAR VERSION:2.0 X-WR-CALNAME:EventsCalendar PRODID:-//hacksw/handcal//NONSGML v1.0//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/New_York LAST-MODIFIED:20240422T053451Z TZURL:https://www.tzurl.org/zoneinfo-outlook/America/New_York X-LIC-LOCATION:America/New_York BEGIN:DAYLIGHT TZNAME:EDT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 DTSTART:19700308T020000 RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU END:DAYLIGHT BEGIN:STANDARD TZNAME:EST TZOFFSETFROM:-0400 TZOFFSETTO:-0500 DTSTART:19701101T020000 RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU END:STANDARD END:VTIMEZONE BEGIN:VEVENT CATEGORIES:College of Engineering,Lectures and Seminars,Thesis/Dissertation s DESCRIPTION:Topic: Development and Testing of Analog Hardware for Training Neural Networks Abstract: As the complexity of Neural Networks increase s, off-chip training computation becomes expensive, and training time incr eases significantly as the dataset size grows. The advantage of on-chip an alog training is the ability to use parallelism by training multiple neuro ns simultaneously, and convergence speed is limited only by the speed of t he analog electronics used in the system. A three-layer Artificial Neural Networks (ANN) architecture was implemented for recognizing handwritten nu mber patterns from the Modified National Institute of Standards and Techno logy (MNIST) database. The system utilizes analog feedback circuits, imple mented on a breadboard, to continuously adjust the Output Layer Neuron (OL N) weights during training mode, establishing real-time on-chip training. This work expands beyond the previous two-neuron ANN system by increasing the number of OLNs to evaluate the scalability and parallelism of on-chip analog training. Successful on-chip training was validated through converg ence of the training weights while each neuron correctly recognized its as signed number and ignored the remaining digits. The results show that the system maintains consistent training behavior as the network size increase s, highlighting the potential of scalable analog on-chip training for neur al networks. Advisor(s): Dr. David P. Rancour, Associate Professor, Dept . of Electrical & Computer Engineering, UMass Dartmouth Committee Member s: Dr. Ruolin Zhou, Associate Professor, Dept. of Electrical & Computer En gineering, UMass Dartmouth; Mr. Joseph Yu Zhu, Electrical Engineering, Ray theon, Portsmouth, RI NOTE: All ECE Graduate Students are ENCOURAGED to attend. All interested parties are invited to attend. Open to the public. *For further information, please contact Dr. David P. Rancour email at drancour@umassd.edu\nEvent page: https://www.umassd.edu/events/cms/7-10-26 -ele-master-of-science-thesis-defense-by-daryon-calhoun---ece.php\nEvent l ink: https://umassd.zoom.us/j/93142092789 X-ALT-DESC;FMTTYPE=text/html:

Topic: Development and Testing of Analog Hardware for Training Neural Networks

Abstract: As th e complexity of Neural Networks increases\, off-chip training computation becomes expensive\, and training time increases significantly as the datas et size grows. The advantage of on-chip analog training is the ability to use parallelism by training multiple neurons simultaneously\, and converge nce speed is limited only by the speed of the analog electronics used in t he system. A three-layer Artificial Neural Networks (ANN) architecture was implemented for recognizing handwritten number patterns from the Modified National Institute of Standards and Technology (MNIST) database. The syst em utilizes analog feedback circuits\, implemented on a breadboard\, to co ntinuously adjust the Output Layer Neuron (OLN) weights during training mo de\, establishing real-time on-chip training. This work expands beyond the previous two-neuron ANN system by increasing the number of OLNs to evalua te the scalability and parallelism of on-chip analog training. Successful on-chip training was validated through convergence of the training weights while each neuron correctly recognized its assigned number and ignored th e remaining digits. The results show that the system maintains consistent training behavior as the network size increases\, highlighting the potenti al of scalable analog on-chip training for neural networks.

Advi sor(s): Dr. David P. Rancour\, Associate Professor\, Dept. of Electrical & Computer Engineering\, UMass Dartmouth

Committee Members: Dr. R uolin Zhou\, Associate Professor\, Dept. of Electrical & Computer Engineer ing\, UMass Dartmouth\; Mr. Joseph Yu Zhu\, Electrical Engineering\, Rayth eon\, Portsmouth\, RI

NOTE: All ECE Graduate Students are ENCOUR AGED to attend. All interested parties are invited to attend. Open to the public.

*For further information\, please contact Dr. David P. R ancour email at drancour@umassd.edu

Event page: https://ww w.umassd.edu/events/cms/7-10-26-ele-master-of-science-thesis-defense-by-da ryon-calhoun---ece.php
Event link: https://umassd.zoom.us/j/93142092789

DTSTAMP:20260626T183636 DTSTART;TZID=America/New_York:20260710T130000 DTEND;TZID=America/New_York:20260710T150000 LOCATION:Charlton College of Business, Room 115 (CCB-115) SUMMARY;LANGUAGE=en-us:ELE Master of Science Thesis Defense by Daryon Calho un - ECE UID:74a02b000d06605d36a63949f0c1536e@www.umassd.edu END:VEVENT END:VCALENDAR